The random pattern testability of programmable logic arrays

An efficient Monte Carlo Algorithm is presented estimating the detection probability of each stuck at fault of a PLA. Furthermore for each primary input of the PLA the optimal probability is computed to set this input to logical "1". Using those unequiprobable input probabilities the necessary test set can be reduced by orders of magnitude. Thus a seIftest by optimized random patterns is possible even if the circuit contains large PLAs preventing a conventional random test

The design of random-testable sequential circuits

A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns

Probabilistische Verfahren für den Test hochintegrierter Schaltungen

Es setzt sich heute immer mehr die Erkenntnis durch, daß anwendungsspezifische hochintegrierte Schaltungen nur dann wirtschaftlich eingesetzt werden können, wenn bereits beim Entwurf die Testerzeugung und Testdurchführung berücksichtigt werden. Um die Ausbildung für den rechnergestützten Schaltungsentwurf an der Fakultät für Informatik der Universität Karlsruhe entsprechend abzurunden, hat der Autor seit dem Wintersemester 1985/1986 die Vorlesung "Testprobleme hochintegrierter Schaltungen" angeboten. Etwa zum gleichen Zeitpunkt etablierte sich am dortigen Institut für Rechnerentwurf und Fehlertoleranz die Forschungsgruppe "Prüfgerechter Entwurf und Test". Das vorliegende Buch vereinigt die Erfahrungen aus der Vorlesung und die Ergebnisse der Forschungsgruppe. Es gibt einen Überblick über wichtige Techniken des prüfgerechten Entwurfs, des Selbsttests sowie der Testerzeugung, und es enthält zahlreiche neue Vorschläge auf diesem Gebiet

Multiple distributions for biased random test patterns

An efficient method has been presented to compute multiple distributions for random patterns, which can be applied successively. Using multiple distributions, all combinational circuits can be made random-testable, and complete fault coverage is provided by a few thousands of random patterns. The differently weighted random test sets can be applied to scan path circuits using an external chip, combining the advantages of a low cost test and of high fault coverage. Several facts about testing by random patterns have been proven. It has been shown that the number of random patterns required for a certain fault coverage can be computed without regarding the pseudorandom property and with the independence assumption for fault detection

On computing optimized input probabilities for random tests

Self testing of integrated circuits by random patterns has several technical and economical advantages. But there exists a large number of circuits which cannot be randomly tested, since the fault coverage achieved that way would be too low. In this paper we show that this problem can be solved by unequiprobable random patterns, and an efficient procedure is presented computing the specific optimal probability for each primary input of a combinational network. Those optimized random patterns can be produced on the chip during self test or off the chip in order to accelerate fault simulation and test pattern generation

Time-optimal control policies for cascaded production-inventory systems with control and state constraints

In this paper time-optimal control policies are derived for models of production-inventory systems consisting of a cascade of basic production- inventory systems with control and state constraints. The analytic solution is due to a decoupling of the complete system into its subsystems by a recursive definition of the cascaded system. It is shown that there is at least one bang-bang controlled subsystem. For the "other" subsystems singular control policies are obtained. Introducing a pseudo-bang-bang control for these systems it is demonstrated that by strengthening the constraints there is a continuous transition from a singular to a bang-bang control

component of this work in other works. Area-Efficient Synthesis of Fault-Secure NoC Switches

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Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits

A method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open faults for M≤n. A hardware architecture is discussed generating this sequence, and for n=1 a built-in self-test (BIST) approach is presented that detects all combinations of multiple combinational and single stuck-open faults. The sequences are of minimum length, and can be produced either by software, by an external chip, or be a BIST-structure. Using the latter, the hardware overhead would be of the same magnitude as a conventional pseudorandom architecture

The pseudoexhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation

Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen

Es wird ein Verfahren vorgestellt, das für die Grundzellen einer Zellbibliothek layoutabhängig die möglichen Fehlfunktionen bestimmt, die durch Fertigungsfehler verursacht werden können. Eingabe für das Verfahren sind neben dem Layout einer Zelle die Prozeßparameter und die Defektverteilungen, Ausgabe sind die realistischen Fehlfunktionen mit ihren Auftrittswahrscheinlichkeiten. Damit können Testerzeugung und Testablauf beschleunigt, schwer testbare Fehler bestimmt und ihre Ursachen lokalisiert und beseitigt werden